Accelerator IP for 5G-NR Polar  Decoder

Polar codes are capacity-approaching codes for the small block lengths, and therefore, are chosen for the 5G-NR control channels. This IP core implements an optimized Polar decoder that is compliant with 5G-NR Polar decoding, 3GPP release 15. 

 

The IP core:

  • implements simplified successive cancellation decoding,
  • supports code lengths of up to 512 bits,
  • significantly improves latency and throughput of the decoder by implementing radix-n F and G accelerators. 

 

Depending on your requirement, the IP-core deliverable may include:

  • Synthesizable Verilog/SystemVerilog RTL code
  • FPGA bitstream with implementation reports (timing, resource utilization, etc.)
  • Synthesized or placed-and-routed netlist (for ASIC or FPGA)
  • Bit-accurate simulation models (C/MATLAB)
  • Full BER/BLER curves across SNR, frame lengths, and code rates
  • Testbench with representative test vectors and reference outputs
Representative Implementation Results:
  • Node: 65nm CMOS,
  • Peak Throughput: 1 Gbps,
  • Clock Frequency: 300 MHz,
  • Core Area: 0.35 mm2.
* Implementing the IP using a smaller process node, like 40nm, 28nm, or 22nm,  could further increase its throughput and reduce the area footprint.