Accelerating High-Throughput Low-Power Silicon

THE PROBLEM

The Scaling Bottleneck in Advanced CMOS

 

As advanced CMOS implementation become increasingly wire-dominated, performance is limited not by logic density but by:

  • Routing congestion

  • Wire-dominated delay

  • Memory bandwidth constraints

  • Data-movement overhead

In highly parallel compute engines, these factors limit clock frequency, increase power consumption, and restrict scalability. Conventional architectures struggle to sustain tens of Gbps throughput within strict power and area budgets.

 

 

 

THE SOLUTION

Routing-Aware Cross-Layer Co-Design

 

XCEL ASICs addresses these bottlenecks through tightly integrated cross-layer optimization that combines:

  • Algorithm development
  • Interconnect-aware architecture
  • Memory-access restructuring
  • Deep silicon implementation expertise

 

By co-optimizing algorithm, architecture, and implementation, we enable scalable ultra-high-throughput silicon optimized for performance, power, and area efficiency.

PRODUCTS

 

Our current portfolio includes high-performance error-correction IP cores engineered for advanced communication applications. These implementations are developed using routing-aware architectures, cross-layer co-design, and deep physical implementation optimization techniques that extend to other ultra-high-throughput communication and compute systems. Recent innovations include:

 

  1. An ultra-high-throughput WiFi LDPC decoder — designed to meet next-gen connectivity demands,

  2. An area-efficient high-throughput LDPC decoder for 5G-NR with full standard compliance,

  3. A multi-Gbps LDPC decoder for WiGig (60 GHz) wireless systems, 

  4. An optimized 5G-NR polar decoder, engineered for performance and low latency.

LDPC decoder for WiFi 7:

 

XCEL ASICs has developed one of the world’s highest-throughput WiFi-compliant LDPC (low-density parity-check) decoders, achieving less than 1 mm² area footprint on a 28nm process node. This decoder delivers up to 25 Gbps throughput, meeting the performance demands of WiFi 7 (IEEE 802.11be), while maintaining full backward compatibility with WiFi 6 (802.11ax), WiFi 5 (802.11ac), and WiFi 4 (802.11n) standards.

 

5G-NR Compliant LDPC Decoder:

 

XCEL ASICs has developed a high-performance, multi-Gbps Low-Density Parity-Check (LDPC) decoder IP for 5G New Radio (5G NR), supporting all block lengths and both base graphs defined in the 5G NR standard. Leveraging routing-aware co-optimization of algorithms, architecture, and circuits, the decoder delivers high throughput, low latency, and efficient silicon area and energy utilization. It supports scalable implementations across process nodes and meets the demanding data-rate requirements of 5G NR, targeting up to 10 Gbps uplink and 20 Gbps downlink.