5G-NR Compliant LDPC Decoder

This IP core implements an optimized low-density parity-check (LDPC) decoder defined in 5G-NR LDPC decoding, 3GPP release 15. A cross-layer optimization of algorithm, architecture, and circuit provides one the best-reported power, performance, and area results for a 5G-NR LDPC decoder. 

 

The IP core:

  • implements layerd LDPC decoding for faster convergence,

  • supports all code rates for base graph 1,

  • supports all code rates for base graph 2, 

  • has configurable max-iterations input,
  • and implements early termination to save energy. 

 

Depending on your requirement, the IP-core deliverable may include:

  • System Verilog source code,
  • System Verilog testbench,
  • Synthesized netlist,
  • Matlab or C bit-accurate model for simulation,
  • comprehensive documentation.
Test-implementation results:
  • Node : 65nm CMOS,
  • Peak Throughput : 7.1 Gbps,
  • Clock Frequency : 150 MHz,
  • Core Area: 4 mm2.