XCEL ASICs' low-density parity-check (LDPC) decoder IP is one of the world's highest-throughput WiFi-4/5/6/7 (IEEE 802.11n/ac/ax/be) compliant IP. A cross-layer optimization of algorithm, architecture, and circuit has resulted in the best-reported power, performance, and area results for a WiFi-compliant LDPC decoder. 

 

The IP core:

• implements layerd LDPC decoding for faster convergence,

• supports all code rates; 1/2, 2/3, 3/4, 5/6,

• supports all frame lengths; 648, 1296, 1944, 

• has configurable max-iterations input,
• and implements early termination to save energy. 

 

Depending on your requirement, the IP-core deliverable may include:

• System Verilog source code,
• System Verilog testbench,
• Synthesized netlist,
• Matlab or C bit-accurate model for simulation, 
• comprehensive documentation.

Test-implementation results:

• Node : 28nm CMOS,

• Peak Throughput : 24.3 Gbps,

• Clock Frequency : 400 MHz,

• Core Area: 904x904=0.82 mm².