Accelerator IP for WiFi

(IEEE 802.11 n/ac/ax/be) LDPC Decoder

This optimized silicon IP core is designed for IEEE 802.11 n/ac/ax/be (WiFi 4/5/6/7) compliant low-density parity-check (LDPC) decoding and addresses the growing demand for high-throughput solutions in WiFi transceiver chips — with a minimal area footprint. The IP core can meet the stringent 30 Gbps throughput requirements of the latest WiFi 7 (IEEE 802.11be) standard. A cross-layer optimization of algorithm, architecture, and circuit has resulted in the best-reported power, performance, and area results for a WiFi-compliant LDPC decoder. Key features of the IP are:

  • implements layered LDPC decoding for faster convergence,

  • supports all code rates: 1/2, 2/3, 3/4, 5/6,

  • supports all frame lengths: 648, 1296, 1944, 

  • has configurable max-iterations input,
  • and implements early termination to save energy. 

 

Depending on your requirement, the IP-core deliverable may include:

  • Synthesizable Verilog/SystemVerilog RTL code
  • FPGA bitstream with implementation reports (timing, resource utilization, etc.)
  • Synthesized or placed-and-routed netlist (for ASIC or FPGA)
  • Bit-accurate simulation models (C/MATLAB)
  • Full BER/BLER curves across SNR, frame lengths, and code rates
  • Testbench with representative test vectors and reference outputs

 

Representative Implementation Results:
  • Node: 28nm CMOS,
  • Peak Throughput: 24.3 Gbps,
  • Clock Frequency: 400 MHz,
  • Core Area: 904x904=0.82 mm2.
* Implementing the IP using a smaller process node, like 22nm, could further increase its throughput and reduce the area footprint.